The invention relates to a method of manufacturing a semiconductor device whereby a surface of a semiconductor body is covered with an electrically insulating layer and at least two electrical conductors situated next to one another and mutually separated by an interposed dielectric layer are provided on the insulating layer, one of the conductors being formed from a first conductive layer deposited on the insulating layer, after which the upper surface and at least the flank of said one conductor facing towards the other conductor are covered with the dielectric layer, whereupon a second conductive layer is deposited over the entire surface, which second conductive layer exhibits a step corresponding to said flank of the first conductor, and subsequently a mask is formed which defines the second conductor and the second conductor is formed by means of etching from the second conductive layer which lies against the dielectric layer on the flank of the first conductor. The invention also relates to a semiconductor device manufactured by such a method.
The invention is of particular importance for charge coupled devices in which the electrical conductors form the gates or clock electrodes provided very closely together above the CCD channel, serving to control the charge storage and charge transport in the channel. The number of electrodes in this case is usually much greater than two. Besides in CCDs, the invention may also be advantageously applied in other types of semiconductor devices such as, for example, memories in which conductor tracks are present at very small distances from one another. It should accordingly be borne in mind that, although the invention will be explained below with particular reference to a charge coupled device, the use of the invention is not limited to charge coupled devices.
A usual practice in the manufacture of charge coupled devices is to provide the gates in a multilayer wiring in which the gates are provided in a higher wiring (or conductor) layer so as to extend in an overlapping manner to above the gates in a lower wiring layer. It is achieved thereby that the interspacings between the gates are no greater than the thickness of an oxide layer on the flanks of the gates in the lower wiring layer. A major disadvantage of this method is that the capacitances caused by this overlap are considerable and thus also the RC times of the electrodes, so that the transport speed is low. Moreover, the energy consumption or dissipation during operation is high owing to the high capacitance values. To counteract these disadvantages, it has been proposed to provide the gates in a non-overlapping configuration. Various methods are known for manufacturing such a configuration, but they all have the disadvantage that they are comparatively intricate. Thus European Patent 0.209,425 describes a method whereby the second wiring layer is provided so as to overlap the gates in the first wiring layer. Windows are then formed in the second wiring layer above the lower gates, after which the oxide layer coveting the upper surface of the lower gates is removed through these windows. Subsequently the second wiring layer is subjected to an isotropic etching step for forming the gates in the second wiring layer, during which this layer is removed through half its thickness simultaneously with the gates in the lower wiring layer. The overlapping portions of the upper wiring layer are etched at two sides and removed throughout their entire thickness.